Using pulsed-latch scan chains for non-destructive ASIC testing

The use of pulsed-latch scan chains in conjunction with a self-generated clock signal is proposed to avoid a complete synthesis of a scan clock tree and the high current present during abnormal conditions that involve a simultaneous displacement of the registers in conventional scanning. The proposed methodology allows for non-destructive testing, and achieves 47% power savings during data shifts compared to its counterparts using shadow and standard flip-flop-based scan chains, with an increase of only 9% in terms of area against the RTL original design.