Resumen
The Large Hadron Collider (LHC) located at the European Organization for Nuclear Research (CERN) is the largest accelerator in the world, where proton-proton collisions take place at the as-of-today highest energy ever reached. The Large Hadron Collider beauty (LHCb) experiment is located at one of the LHC interaction points, and its detector and readout electronics are currently able to cope with the 40 MHz bunch crossing rate, corresponding to 4 TB/s. A software-only trigger, with the first stage (High-Level Trigger 1) completely running on Graphics Processing Units (GPU) cards, reduces the data rate to 10 GB/s performing partial detector reconstruction and selection. Advanced computing techniques are being used and developed to accelerate information analysis. In this paper, we discuss, and show the first results of a GPU-based sequence for the reconstruction of the LHCb Ring Imaging Cherenkov detectors (RICH) that is currently being implemented. An increase in throughput of up to a factor of 172 with respect to the implementation on CPUs and the achieved 81% performance portability show the potential of using this technology for the rest of the detector reconstruction.
Idioma original | Inglés |
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Título de la publicación alojada | 2024 IEEE 42nd Central America and Panama Convention, CONCAPAN 2024 |
Editorial | Institute of Electrical and Electronics Engineers Inc. |
Edición | 2024 |
ISBN (versión digital) | 9798350366723 |
DOI | |
Estado | Publicada - 2024 |
Evento | 42nd IEEE Central America and Panama Convention, CONCAPAN 2024 - San Jose, Costa Rica Duración: 27 nov 2024 → 29 nov 2024 |
Conferencia
Conferencia | 42nd IEEE Central America and Panama Convention, CONCAPAN 2024 |
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País/Territorio | Costa Rica |
Ciudad | San Jose |
Período | 27/11/24 → 29/11/24 |