TY - GEN
T1 - PlasticNet+
T2 - 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
AU - Salazar-García, Carlos
AU - García-Ramírez, Ronny
AU - Rímolo-Donadío, Renato
AU - Strydis, Christos
AU - Chacón-Rodríguez, Alfonso
N1 - Publisher Copyright:
© 2021 IEEE
PY - 2021/5/28
Y1 - 2021/5/28
N2 - This paper addresses the communication challenges posed in multi-FPGA systems, by improving a custom FPGA interconnect architecture via the high-speed transceivers available in modern FPGA development boards. The proposed network interconnection, built upon the PlasticNet architecture, is evaluated using the high-speed serial transceiver in Zynq ZC706 FPGA boards. Results show a best-case latency of only 300 ns, demonstrating equivalent results in terms of latency on a par with the known BlueLink framework, but with the plus of having total re-configurability across the different layers of its network interconnection model. This makes the current proposal a competitive option for the development of distributed, heterogeneous multi-FPGA processing systems.
AB - This paper addresses the communication challenges posed in multi-FPGA systems, by improving a custom FPGA interconnect architecture via the high-speed transceivers available in modern FPGA development boards. The proposed network interconnection, built upon the PlasticNet architecture, is evaluated using the high-speed serial transceiver in Zynq ZC706 FPGA boards. Results show a best-case latency of only 300 ns, demonstrating equivalent results in terms of latency on a par with the known BlueLink framework, but with the plus of having total re-configurability across the different layers of its network interconnection model. This makes the current proposal a competitive option for the development of distributed, heterogeneous multi-FPGA processing systems.
KW - Axi4
KW - Custom FPGA networks
KW - Hls
KW - inter-FPGA communication
KW - Interconnect architecture
KW - multi-FPGA distributed processing
KW - Custom FPGA
KW - HLS
KW - AXI4
KW - interconnect architecture
KW - inter-FPGA communication
KW - multi-FPGA distributed processing
KW - networks
UR - http://www.scopus.com/inward/record.url?scp=85108994627&partnerID=8YFLogxK
U2 - 10.1109/ISCAS51556.2021.9401058
DO - 10.1109/ISCAS51556.2021.9401058
M3 - Contribución a la conferencia
AN - SCOPUS:85108994627
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1
EP - 5
BT - IEEE International Symposium on Circuits and Systems (ISCAS)
PB - Institute of Electrical and Electronics Engineers Inc.
CY - Daegu, Corea
Y2 - 22 May 2021 through 28 May 2021
ER -