TY - GEN
T1 - Asynchronous staggered set/reset techniques for low-noise applications
AU - Rimolo-Donadio, Renato
AU - Acosta, Antonio J.
AU - Krautschneider, Wolfgang
PY - 2007
Y1 - 2007
N2 - This work proposes the usage of staggered initialization schemes in digital sequential circuits as complementary technique to reduce the simultaneous switching activity, pursuing the minimization of switching noise levels. Simultaneous switching noise (SSN) generation has been evaluated in digital sequential circuits during initialization and a general synthesis methodology has been proposed in order to implement the staggered initialization schemes at system level. The evaluation of this methodology was made with counter arrays using 0.35μm AMS library cells. In addition, timing considerations, clock suppression during initialization cycles, and the type of cell chosen to implement the staggered distribution are discussed. Main results include noise reduction levels, by suppression of power supply fluctuations, up to 66.7% in post-layout simulations when using staggered techniques enhanced with clock gating during initialization.
AB - This work proposes the usage of staggered initialization schemes in digital sequential circuits as complementary technique to reduce the simultaneous switching activity, pursuing the minimization of switching noise levels. Simultaneous switching noise (SSN) generation has been evaluated in digital sequential circuits during initialization and a general synthesis methodology has been proposed in order to implement the staggered initialization schemes at system level. The evaluation of this methodology was made with counter arrays using 0.35μm AMS library cells. In addition, timing considerations, clock suppression during initialization cycles, and the type of cell chosen to implement the staggered distribution are discussed. Main results include noise reduction levels, by suppression of power supply fluctuations, up to 66.7% in post-layout simulations when using staggered techniques enhanced with clock gating during initialization.
UR - https://www.scopus.com/pages/publications/34548862088
U2 - 10.1109/iscas.2007.378022
DO - 10.1109/iscas.2007.378022
M3 - Contribución a la conferencia
AN - SCOPUS:34548862088
SN - 1424409209
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1799
EP - 1802
BT - 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
Y2 - 27 May 2007 through 30 May 2007
ER -