Resumen
One approach that has been suggested to further reduce the energy consumption of heterogenous Systems-on-Chip (SoCs) is approximate computing. In approximate computing the error at the output is relaxed in order to simplify the hardware and thus, achieve lowerpower. Fortunately, most of the hardware accelerators in these SoCs are also amenable to approximate computing.
In this work we propose a fully automatic method that substitutes portions of a hardware accelerator specified in C/C++/SystemC for
High-Level Synthesis (HLS) to an Artificial Neural Network (ANN).
ANNs have many advantages that make them well suited for this.
First, they are very scalable which allows to approximate multiple separate portions of the behavioral description simultaneously on them. Second, multiple ANNs can be fused together and reoptimized to further reduce the power consumption. We use this to share the ANN to approximate multiple different HW accelerators in the same SoC . Experimental results with different error thresholds show that our proposed approach leads to better results than the state of the art.
In this work we propose a fully automatic method that substitutes portions of a hardware accelerator specified in C/C++/SystemC for
High-Level Synthesis (HLS) to an Artificial Neural Network (ANN).
ANNs have many advantages that make them well suited for this.
First, they are very scalable which allows to approximate multiple separate portions of the behavioral description simultaneously on them. Second, multiple ANNs can be fused together and reoptimized to further reduce the power consumption. We use this to share the ANN to approximate multiple different HW accelerators in the same SoC . Experimental results with different error thresholds show that our proposed approach leads to better results than the state of the art.
Idioma original | Inglés |
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Título de la publicación alojada | ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference |
Lugar de publicación | Tokyo, Japan |
Editorial | Institute of Electrical and Electronics Engineers Inc. |
Páginas | 410-415 |
Número de páginas | 6 |
ISBN (versión digital) | 9781450397834 |
DOI | |
Estado | Publicada - 16 ene 2023 |
Evento | 28th Asia and South Pacific Design Automation Conference, ASP-DAC 2023 - Tokyo, Japón Duración: 16 ene 2023 → 19 ene 2023 |
Serie de la publicación
Nombre | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC |
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Conferencia
Conferencia | 28th Asia and South Pacific Design Automation Conference, ASP-DAC 2023 |
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País/Territorio | Japón |
Ciudad | Tokyo |
Período | 16/01/23 → 19/01/23 |