Acceleration of Fully Connected Layers on FPGA using the Strassen Matrix Multiplication

Deep Learning is one of the most popular techniques of Machine Learning (ML) but also one of the most computationally intensive and energy-demanding task in High-Performance Computing (HPC), resulting in concerns about the sustainability of executing Artificial Intelligence massively. The challenge becomes harder when performing inference tasks at the Edge, where computational resources and energy are scarce. Field Programmable Gate Arrays (FPGAs) are hardware-level reconfigurable devices with greater benefits in computer power vs energy consumption compared to CPUs and GPUs in the wide spectrum of HPC. High-Level Synthesis has helped reduce the complexity of using FPGAs to accelerate algorithms using high-level languages like C++. This opens opportunities to research new hardware architectures for accelerating Deep Learning Inference (DLI) using FPGAs for energy-constraint applications. Most ML applications involve Deep Neural Networks (DNNs), where matrix multiplication is one of the most popular operations. This work covers the optimisation of matrix multiplication by proposing a generic, HLS-compliant Strassen Matrix Multiplication Processing Element (PE) capable of adapting its implementation under different numerical precisions and hardware approximations. We discuss the PE's numerical and resource consumption analysis under several configurations and describe how it behaves in an actual DNN model dedicated to anomaly detection, spotting promising results for FPGA-based DLI at the Edge, saving up to 12.5% of DSP cells compared to the standard multiplication units on an XC7A50T (low-end FPGA) with negligible accuracy loss.