Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation

Andres Malavasi-Mora; Renato Rimolo-Donadio

doi:10.1109/LASCAS45839.2020.9069016

Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation

Andres Malavasi-Mora
, Renato Rimolo-Donadio

Escuela de Ingeniería Electrónica

Intel Labs

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

High-frequency power supply noise compromises performance and energy efficiency of microprocessor-based products, restricting the maximum frequency of operation for electronic systems and decreasing device reliability. A guard band needs to be set in order to tolerate voltage drops without having any execution problem but leading to a performance reduction. This work proposes a technique to enhance voltage drop tolerance through adaptive scaling, taking advantage of the clock-data compensation effect. The proposed solution is validated with test cases in a FinFet CMOS technology at a post-layout simulation level, reaching from 6% up to 30% more voltage drop tolerance.

Original language	English
Title of host publication	2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728134277
DOIs	https://doi.org/10.1109/LASCAS45839.2020.9069016
State	Published - Feb 2020
Event	11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020 - San Jose, Costa Rica Duration: 25 Feb 2020 → 28 Feb 2020

Publication series

Name	2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020

Conference

Conference	11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020
Country/Territory	Costa Rica
City	San Jose
Period	25/02/20 → 28/02/20

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Adaptive voltage scaling
CMOS circuit
clock-data compensation
power noise
voltage drop.

Access to Document

10.1109/LASCAS45839.2020.9069016

Cite this

Malavasi-Mora, A., & Rimolo-Donadio, R. (2020). Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation. In 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020 Article 9069016 (2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/LASCAS45839.2020.9069016

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title = "Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation",

abstract = "High-frequency power supply noise compromises performance and energy efficiency of microprocessor-based products, restricting the maximum frequency of operation for electronic systems and decreasing device reliability. A guard band needs to be set in order to tolerate voltage drops without having any execution problem but leading to a performance reduction. This work proposes a technique to enhance voltage drop tolerance through adaptive scaling, taking advantage of the clock-data compensation effect. The proposed solution is validated with test cases in a FinFet CMOS technology at a post-layout simulation level, reaching from 6\% up to 30\% more voltage drop tolerance.",

keywords = "Adaptive voltage scaling, CMOS circuit, clock-data compensation, power noise, voltage drop.",

author = "Andres Malavasi-Mora and Renato Rimolo-Donadio",

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year = "2020",

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Malavasi-Mora, A & Rimolo-Donadio, R 2020, Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation. in 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020., 9069016, 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020, Institute of Electrical and Electronics Engineers Inc., 11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020, San Jose, Costa Rica, 25/02/20. https://doi.org/10.1109/LASCAS45839.2020.9069016

Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation. / Malavasi-Mora, Andres; Rimolo-Donadio, Renato.
2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9069016 (2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation

AU - Malavasi-Mora, Andres

AU - Rimolo-Donadio, Renato

PY - 2020/2

Y1 - 2020/2

N2 - High-frequency power supply noise compromises performance and energy efficiency of microprocessor-based products, restricting the maximum frequency of operation for electronic systems and decreasing device reliability. A guard band needs to be set in order to tolerate voltage drops without having any execution problem but leading to a performance reduction. This work proposes a technique to enhance voltage drop tolerance through adaptive scaling, taking advantage of the clock-data compensation effect. The proposed solution is validated with test cases in a FinFet CMOS technology at a post-layout simulation level, reaching from 6% up to 30% more voltage drop tolerance.

AB - High-frequency power supply noise compromises performance and energy efficiency of microprocessor-based products, restricting the maximum frequency of operation for electronic systems and decreasing device reliability. A guard band needs to be set in order to tolerate voltage drops without having any execution problem but leading to a performance reduction. This work proposes a technique to enhance voltage drop tolerance through adaptive scaling, taking advantage of the clock-data compensation effect. The proposed solution is validated with test cases in a FinFet CMOS technology at a post-layout simulation level, reaching from 6% up to 30% more voltage drop tolerance.

KW - Adaptive voltage scaling

KW - CMOS circuit

KW - clock-data compensation

KW - power noise

KW - voltage drop.

UR - https://www.scopus.com/pages/publications/85084300259

U2 - 10.1109/LASCAS45839.2020.9069016

DO - 10.1109/LASCAS45839.2020.9069016

M3 - Contribución a la conferencia

AN - SCOPUS:85084300259

T3 - 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020

BT - 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020

Y2 - 25 February 2020 through 28 February 2020

ER -

Malavasi-Mora A, Rimolo-Donadio R. Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation. In 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020. Institute of Electrical and Electronics Engineers Inc. 2020. 9069016. (2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020). doi: 10.1109/LASCAS45839.2020.9069016

Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation

Abstract

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UN SDGs

Keywords

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