Using pulsed-latch scan chains for non-destructive ASIC testing

Bernardo Rodriguez-Hall; Alfonso Chacon-Rodriguez; Renato Rimolo-Donadio; Ronny García-Ramírez

doi:10.1109/concapan63470.2024.10933830

Using pulsed-latch scan chains for non-destructive ASIC testing

Escuela de Ingeniería Electrónica

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The use of pulsed-latch scan chains in conjunction with a self-generated clock signal is proposed to avoid a complete synthesis of a scan clock tree and the high current present during abnormal conditions that involve a simultaneous displacement of the registers in conventional scanning. The proposed methodology allows for non-destructive testing, and achieves 47% power savings during data shifts compared to its counterparts using shadow and standard flip-flop-based scan chains, with an increase of only 9% in terms of area against the RTL original design.

Translated title of the contribution	Uso de cadenas de escaneo de pestillo pulsado para pruebas ASIC no destructivas
Original language	English
Title of host publication	2024 IEEE 42nd Central America and Panama Convention (CONCAPAN XLII)
Publisher	Institute of Electrical and Electronics Engineers Inc.
Edition	2024
ISBN (Electronic)	9798350366723
DOIs	https://doi.org/10.1109/concapan63470.2024.10933830 https://doi.org/10.1109/CONCAPAN63470.2024.10933830
State	Published - 27 Nov 2024
Event	42nd IEEE Central America and Panama Convention, CONCAPAN 2024 - San Jose, Costa Rica Duration: 27 Nov 2024 → 29 Nov 2024

Conference

Conference	42nd IEEE Central America and Panama Convention, CONCAPAN 2024
Country/Territory	Costa Rica
City	San Jose
Period	27/11/24 → 29/11/24

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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Rodriguez-Hall, B., Chacon-Rodriguez, A., Rimolo-Donadio, R., & García-Ramírez, R. (2024). Using pulsed-latch scan chains for non-destructive ASIC testing. In 2024 IEEE 42nd Central America and Panama Convention (CONCAPAN XLII) (2024 ed.). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/concapan63470.2024.10933830, https://doi.org/10.1109/CONCAPAN63470.2024.10933830

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abstract = "The use of pulsed-latch scan chains in conjunction with a self-generated clock signal is proposed to avoid a complete synthesis of a scan clock tree and the high current present during abnormal conditions that involve a simultaneous displacement of the registers in conventional scanning. The proposed methodology allows for non-destructive testing, and achieves 47\% power savings during data shifts compared to its counterparts using shadow and standard flip-flop-based scan chains, with an increase of only 9\% in terms of area against the RTL original design.",

keywords = "Design for test, pulsed latch, scan chains, Observability",

author = "Bernardo Rodriguez-Hall and Alfonso Chacon-Rodriguez and Renato Rimolo-Donadio and Ronny Garc{\'i}a-Ram{\'i}rez",

note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 42nd IEEE Central America and Panama Convention, CONCAPAN 2024 ; Conference date: 27-11-2024 Through 29-11-2024",

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Rodriguez-Hall, B, Chacon-Rodriguez, A , Rimolo-Donadio, R & García-Ramírez, R 2024, Using pulsed-latch scan chains for non-destructive ASIC testing. in 2024 IEEE 42nd Central America and Panama Convention (CONCAPAN XLII). 2024 edn, Institute of Electrical and Electronics Engineers Inc., 42nd IEEE Central America and Panama Convention, CONCAPAN 2024, San Jose, Costa Rica, 27/11/24. https://doi.org/10.1109/concapan63470.2024.10933830, https://doi.org/10.1109/CONCAPAN63470.2024.10933830

Using pulsed-latch scan chains for non-destructive ASIC testing. / Rodriguez-Hall, Bernardo; Chacon-Rodriguez, Alfonso ; Rimolo-Donadio, Renato et al.
2024 IEEE 42nd Central America and Panama Convention (CONCAPAN XLII). 2024. ed. Institute of Electrical and Electronics Engineers Inc., 2024.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Using pulsed-latch scan chains for non-destructive ASIC testing

AU - Rodriguez-Hall, Bernardo

AU - Chacon-Rodriguez, Alfonso

AU - Rimolo-Donadio, Renato

AU - García-Ramírez, Ronny

PY - 2024/11/27

Y1 - 2024/11/27

N2 - The use of pulsed-latch scan chains in conjunction with a self-generated clock signal is proposed to avoid a complete synthesis of a scan clock tree and the high current present during abnormal conditions that involve a simultaneous displacement of the registers in conventional scanning. The proposed methodology allows for non-destructive testing, and achieves 47% power savings during data shifts compared to its counterparts using shadow and standard flip-flop-based scan chains, with an increase of only 9% in terms of area against the RTL original design.

AB - The use of pulsed-latch scan chains in conjunction with a self-generated clock signal is proposed to avoid a complete synthesis of a scan clock tree and the high current present during abnormal conditions that involve a simultaneous displacement of the registers in conventional scanning. The proposed methodology allows for non-destructive testing, and achieves 47% power savings during data shifts compared to its counterparts using shadow and standard flip-flop-based scan chains, with an increase of only 9% in terms of area against the RTL original design.

KW - Design for test

KW - pulsed latch

KW - scan chains

KW - Observability

UR - https://www.scopus.com/pages/publications/105005864933

U2 - 10.1109/concapan63470.2024.10933830

DO - 10.1109/concapan63470.2024.10933830

M3 - Contribución a la conferencia

BT - 2024 IEEE 42nd Central America and Panama Convention (CONCAPAN XLII)

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 42nd IEEE Central America and Panama Convention, CONCAPAN 2024

Y2 - 27 November 2024 through 29 November 2024

ER -

Using pulsed-latch scan chains for non-destructive ASIC testing

Abstract

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UN SDGs

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