Ultra-Compact Approximate 4:2 Compressor on the Design of Power-Efficient Multipliers for Image Multiplication

This work proposes the adoption of an energy-efficient approximate 4:2 compressor at the transistor level for designing a Dadda tree approximate multiplier. The proposal is also evaluated considering eight other state-of-the-art approximate compressors. Our MAX4:2CV2-based multiplier proposal reduces delay by up to 50.4%, power consumption by up to 59.2%, and Power-Delay Product (PDP) by up to 79.7% compared to an exact multiplier. Furthermore, we evaluate the multiplier quality through pixel-by-pixel image multiplication, where we observe an acceptable result of 31 dB on average for the Peak Signal-to-Noise Ratio (PSNR). These findings highlight that the adoption of the proposed compressor can improve the efficiency of approximate multiplier designs, especially when area and power savings are a critical factor.