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The viability of 25 Gb/s on-board signalling

  • Mark B. Ritter
  • , Petar Pepeljugoski
  • , Xiaoxiong Gu
  • , Young Kwark
  • , Dong Kam
  • , Renato Rimolo-Donadio
  • , Boping Wu
  • , Christian Baks
  • , Richard John
  • , Lei Shan
  • , Christian Schuster

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

What package improvements are required for dense, high aggregate bandwidth buses running at data rates beyond 10 Gb/s per pin, and when might optical interconnects on the board be required? We present a study of distance and speed limits for electrical on-board module-to-module links with an eye to answering these questions. Detailed electrical link models have been validated with active, high-speed differential bus measurements utilizing a 16-channel link chip with programmable equalization and a per-channel data rate of up to 11 Gb/s. Electrical signalling limits were then determined by extrapolating our models to higher speeds, and these limits were compared to the results of work on on-board optical interconnects.

Original languageEnglish
Title of host publication2008 Proceedings 58th Electronic Components and Technology Conference, ECTC
Pages1121-1127
Number of pages7
DOIs
StatePublished - 2008
Externally publishedYes
Event2008 58th Electronic Components and Technology Conference, ECTC - Lake Buena Vista, FL, United States
Duration: 27 May 200830 May 2008

Publication series

NameProceedings - Electronic Components and Technology Conference
ISSN (Print)0569-5503

Conference

Conference2008 58th Electronic Components and Technology Conference, ECTC
Country/TerritoryUnited States
CityLake Buena Vista, FL
Period27/05/0830/05/08

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