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Review of CMOS circuit architectures for Electrical Impedance Spectroscopy

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

In this paper, different architectures at integrated circuit level for the implementation of Electrical Impedance Spectroscopy(EIS) systems are compared and discused. The main functional blocks required by each architecture and their underlying concepts are explained. Additionally, the performance and design specifications for different implementations are contrasted.

Original languageEnglish
Title of host publication2016 IEEE 36th Central American and Panama Convention, CONCAPAN 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467395786
DOIs
StatePublished - 2 Jul 2016
Event36th IEEE Central American and Panama Convention, CONCAPAN 2016 - San Jose, Costa Rica
Duration: 9 Nov 201611 Nov 2016

Publication series

Name2016 IEEE 36th Central American and Panama Convention, CONCAPAN 2016

Conference

Conference36th IEEE Central American and Panama Convention, CONCAPAN 2016
Country/TerritoryCosta Rica
CitySan Jose
Period9/11/1611/11/16

Keywords

  • Broadband Impedance Spectroscopy
  • CMOS Circuits
  • Electric Impedance Spectroscopy
  • Impedance
  • Spectroscopy

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