@inproceedings{657e8f2647384fcea81a7fa5f3fa2cce,
title = "Integrated circuit with memristor emulator array and neuron circuits for neuromorphic pattern recognition",
abstract = "This paper details an array of switch resistor based memristor emulators with integrate \& fire based neuron ASIC for the development of memristor based pattern recognition. The designed ASIC has 4 memristor emulators with a conductance range from 195 nS to 190 uS; processing has been planned to be off-chip to get the freedom of programmability of any function in ASIC. The ASIC has 2 integrate and fire (I \& F) neuron circuits which are planned to be used in conjunction with memristors in a large multiple chip network for pattern recognition. This paper explains the memristor emulator, I \& F neurons and an algorithm of pattern recognition simulated in Ltspice. The ASIC has been fabricated in AMS 350nm process.",
keywords = "ASIC, Emulator, Memristor, Neuron, Pattern recognition",
author = "Rajeev Ranjan and Alexandros Kyrmanidis and Hellweg, \{Wolf Lukas\} and Ponce, \{Pablo Mendoza\} and Saleh, \{Lait Abu\} and Dietmar Schroeder and Krautschneider, \{Wolfgang H.\}",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 39th International Conference on Telecommunications and Signal Processing, TSP 2016 ; Conference date: 27-06-2016 Through 29-06-2016",
year = "2016",
month = nov,
day = "28",
doi = "10.1109/TSP.2016.7760875",
language = "Ingl{\'e}s",
series = "2016 39th International Conference on Telecommunications and Signal Processing, TSP 2016",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "265--268",
editor = "Norbert Herencsar",
booktitle = "2016 39th International Conference on Telecommunications and Signal Processing, TSP 2016",
}