TY - GEN
T1 - Evaluation of 8b/10b FPGA Encoder Implementations for SerDes Links
AU - Quesada-Martinez, Andres
AU - Aparicio-Morales, Javier
AU - Campos-Araya, Jose
AU - Chacon-Rodriguez, Alfonso
AU - Garcia-Ramirez, Ronny
AU - Rimolo-Donadio, Renato
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/2
Y1 - 2020/2
N2 - In this work, alternatives to implement 8b/10b encoders in FPGAs for serializer-deserializer links are evaluated. Custom implementations based on decoders and look-up tables are benchmarked, and then compared against an implementation based on a commercial IP. The evaluation is performed in terms of area, power consumption, timing margins, and required resources. The used hardware is a Kintex-7 evaluation board with an external 600 MHz clock reference, where a basic transceiver including scramblers, the encoders, and a serializer/deserializer was implemented. Results show that custom implementations are much more compact and consume less than 50% of power in comparison to the IP-based implementation per lane usage, at the cost of reduced functionalities.
AB - In this work, alternatives to implement 8b/10b encoders in FPGAs for serializer-deserializer links are evaluated. Custom implementations based on decoders and look-up tables are benchmarked, and then compared against an implementation based on a commercial IP. The evaluation is performed in terms of area, power consumption, timing margins, and required resources. The used hardware is a Kintex-7 evaluation board with an external 600 MHz clock reference, where a basic transceiver including scramblers, the encoders, and a serializer/deserializer was implemented. Results show that custom implementations are much more compact and consume less than 50% of power in comparison to the IP-based implementation per lane usage, at the cost of reduced functionalities.
KW - 8b/10b Encoding
KW - FPGA
KW - Interconnects
KW - SerDes
KW - Serial Links
UR - https://www.scopus.com/pages/publications/85084298245
U2 - 10.1109/LASCAS45839.2020.9069001
DO - 10.1109/LASCAS45839.2020.9069001
M3 - Contribución a la conferencia
AN - SCOPUS:85084298245
T3 - 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
BT - 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020
Y2 - 25 February 2020 through 28 February 2020
ER -