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Design of an IDM-based determinant computing unit for a 130nm low power CMOS ASIC acoustic localization processor

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A determinant computing circuit in floating point format has been designed and tested for use in a CMOS ASIC acoustic localization processor. The Internal Division Method (IDM) was used to implement the operation, employing a modified SRT radix-4 circuit for division operations. The unit was designed for VLSI implementation in a commercial 130nm low-power CMOS process, with an operation frequency of 100MHz. The algorithm employed is parallelizable for future prototypes, should a higher operation frequency be required.

Original languageEnglish
Title of host publication2015 IEEE 6th Latin American Symposium on Circuits and Systems, LASCAS 2015 - Conference Proceedings
EditorsAlfredo Arnaud, Fernando Silveira, Lorena Garcia
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479983322
DOIs
StatePublished - 9 Sep 2015
Event6th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2015 - Montevideo, Uruguay
Duration: 24 Feb 201527 Feb 2015

Publication series

Name2015 IEEE 6th Latin American Symposium on Circuits and Systems, LASCAS 2015 - Conference Proceedings

Conference

Conference6th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2015
Country/TerritoryUruguay
CityMontevideo
Period24/02/1527/02/15

Keywords

  • Acoustic Localization
  • FPGA
  • Low Power VLSI
  • Multichannel Cross Correlation Coefficient
  • TDOA
  • UVM

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