Design of a MCML gate library applying multiobjective optimization

Roberto Pereira-Arroyo; Pablo Alvarado-Moya; Wolfgang H. Krautschneider

doi:10.1109/ISVLSI.2007.38

Design of a MCML gate library applying multiobjective optimization

Roberto Pereira-Arroyo
, Pablo Alvarado-Moya
, Wolfgang H. Krautschneider

Escuela de Ingeniería Electrónica

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of each gate that is part of our MCML basic library. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Measures of the power consumption, propagation delay and output voltage swing are used as fitness functions, since the problem is treated as a multiobjective optimization task. Finally, the results of postlayout simulations, using the AMS 0.35 μm technology are presented.

Original language	English
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publication	Emerging VLSI Technologies and Architectures
Pages	81-85
Number of pages	5
DOIs	https://doi.org/10.1109/ISVLSI.2007.38
State	Published - 2007
Event	IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07 - Porto Alegre, Brazil Duration: 9 Mar 2007 → 11 Mar 2007

Publication series

Name	Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Conference

Conference	IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07
Country/Territory	Brazil
City	Porto Alegre
Period	9/03/07 → 11/03/07

Keywords

Design space exploration
Genetic algorithms
MOS current mode logic (MCML)
Multi-objective optimization
Pareto front

Access to Document

10.1109/ISVLSI.2007.38

Cite this

Pereira-Arroyo, R., Alvarado-Moya, P., & Krautschneider, W. H. (2007). Design of a MCML gate library applying multiobjective optimization. In Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (pp. 81-85). Article 4208898 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures). https://doi.org/10.1109/ISVLSI.2007.38

Pereira-Arroyo, Roberto ; Alvarado-Moya, Pablo ; Krautschneider, Wolfgang H. / Design of a MCML gate library applying multiobjective optimization. Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures. 2007. pp. 81-85 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures).

@inproceedings{e1878bd3827145988e838e85d23ace70,

title = "Design of a MCML gate library applying multiobjective optimization",

abstract = "In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of each gate that is part of our MCML basic library. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Measures of the power consumption, propagation delay and output voltage swing are used as fitness functions, since the problem is treated as a multiobjective optimization task. Finally, the results of postlayout simulations, using the AMS 0.35 μm technology are presented.",

keywords = "Design space exploration, Genetic algorithms, MOS current mode logic (MCML), Multi-objective optimization, Pareto front",

author = "Roberto Pereira-Arroyo and Pablo Alvarado-Moya and Krautschneider, \{Wolfgang H.\}",

year = "2007",

doi = "10.1109/ISVLSI.2007.38",

language = "Ingl{\'e}s",

isbn = "0769528961",

series = "Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures",

pages = "81--85",

booktitle = "Proceedings - IEEE Computer Society Annual Symposium on VLSI",

note = "IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07 ; Conference date: 09-03-2007 Through 11-03-2007",

}

Pereira-Arroyo, R, Alvarado-Moya, P & Krautschneider, WH 2007, Design of a MCML gate library applying multiobjective optimization. in Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures., 4208898, Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, pp. 81-85, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07, Porto Alegre, Brazil, 9/03/07. https://doi.org/10.1109/ISVLSI.2007.38

Design of a MCML gate library applying multiobjective optimization. / Pereira-Arroyo, Roberto; Alvarado-Moya, Pablo; Krautschneider, Wolfgang H.
Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures. 2007. p. 81-85 4208898 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design of a MCML gate library applying multiobjective optimization

AU - Pereira-Arroyo, Roberto

AU - Alvarado-Moya, Pablo

AU - Krautschneider, Wolfgang H.

PY - 2007

Y1 - 2007

N2 - In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of each gate that is part of our MCML basic library. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Measures of the power consumption, propagation delay and output voltage swing are used as fitness functions, since the problem is treated as a multiobjective optimization task. Finally, the results of postlayout simulations, using the AMS 0.35 μm technology are presented.

AB - In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of each gate that is part of our MCML basic library. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Measures of the power consumption, propagation delay and output voltage swing are used as fitness functions, since the problem is treated as a multiobjective optimization task. Finally, the results of postlayout simulations, using the AMS 0.35 μm technology are presented.

KW - Design space exploration

KW - Genetic algorithms

KW - MOS current mode logic (MCML)

KW - Multi-objective optimization

KW - Pareto front

UR - https://www.scopus.com/pages/publications/36348969303

U2 - 10.1109/ISVLSI.2007.38

DO - 10.1109/ISVLSI.2007.38

M3 - Contribución a la conferencia

AN - SCOPUS:36348969303

SN - 0769528961

SN - 9780769528960

T3 - Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

SP - 81

EP - 85

BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI

T2 - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07

Y2 - 9 March 2007 through 11 March 2007

ER -

Pereira-Arroyo R, Alvarado-Moya P, Krautschneider WH. Design of a MCML gate library applying multiobjective optimization. In Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures. 2007. p. 81-85. 4208898. (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures). doi: 10.1109/ISVLSI.2007.38

Design of a MCML gate library applying multiobjective optimization

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