TY - GEN
T1 - Challenges for High Volume Testing of Embedded IO Interfaces in Disaggregated Microprocessor Products
AU - Garita-Rodriguez, Esteban
AU - Rimolo-Donadio, Renato
AU - Zamora-Salazar, Rafael
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - The high-performance microprocessor industry is moving towards the paradigm of heterogeneously integrated IC products, as an alternative to offer more customizable solutions to different market segments at a more rapid pace. This approach involves the use of many dice in combination with advanced 2.5 and 3D packaging technologies, where the continuous scaling-down of silicon processes imposes new challenges in terms of process control and assembly reliability. This translates to new test requirements and methods to handle the parallel-massive IO interfaces that are needed to communicate across all dice. In this paper, we review the main approaches and considerations for testing embedded interfaces over silicon bridges in high-volume environments. The Wafer Level Test phase and Final Package Test are discussed, together with the strategies to differentiate silicon and assembly induced fails, repair capabilities, and system margin validation features. Finally, an overview of future challenges for next generation products is provided.
AB - The high-performance microprocessor industry is moving towards the paradigm of heterogeneously integrated IC products, as an alternative to offer more customizable solutions to different market segments at a more rapid pace. This approach involves the use of many dice in combination with advanced 2.5 and 3D packaging technologies, where the continuous scaling-down of silicon processes imposes new challenges in terms of process control and assembly reliability. This translates to new test requirements and methods to handle the parallel-massive IO interfaces that are needed to communicate across all dice. In this paper, we review the main approaches and considerations for testing embedded interfaces over silicon bridges in high-volume environments. The Wafer Level Test phase and Final Package Test are discussed, together with the strategies to differentiate silicon and assembly induced fails, repair capabilities, and system margin validation features. Finally, an overview of future challenges for next generation products is provided.
KW - chip disaggregation
KW - design for test
KW - embedded IO
KW - final package test
KW - heterogeneous integration
KW - high-volume manufacturing
KW - wafer level test
UR - https://www.scopus.com/pages/publications/85146147363
U2 - 10.1109/ITC50671.2022.00053
DO - 10.1109/ITC50671.2022.00053
M3 - Contribución a la conferencia
AN - SCOPUS:85146147363
T3 - Proceedings - International Test Conference
SP - 456
EP - 464
BT - Proceedings - 2022 IEEE International Test Conference, ITC 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE International Test Conference, ITC 2022
Y2 - 23 September 2022 through 30 September 2022
ER -