TY - GEN
T1 - Backplane channel design optimization
T2 - DesignCon 2012: Where Chipheads Connect
AU - Gu, Xiaoxiong
AU - Kwark, Young H.
AU - Liu, Dazhao
AU - Zhang, Yaojiang
AU - Fan, Jun
AU - Rimolo-Donadio, Renato
AU - Müller, Sebastian
AU - Schuster, Christian
AU - De Paulis, Francesco
PY - 2012
Y1 - 2012
N2 - We start with hardware verified interconnect models based on a 3Gb/s serial link. Stepwise recasting of this single ended link proceeds by peeling off the distortions introduced by lossy dielectric, via stubs, trace and via array cross-talk, and outdated connectors. Equalization schemes (4-tap FFE, 2-stage CTLE, 15-tap DFE) are then applied to demonstrate error-free NRZ signaling at 25Gb/s over the rehabilitated link.
AB - We start with hardware verified interconnect models based on a 3Gb/s serial link. Stepwise recasting of this single ended link proceeds by peeling off the distortions introduced by lossy dielectric, via stubs, trace and via array cross-talk, and outdated connectors. Equalization schemes (4-tap FFE, 2-stage CTLE, 15-tap DFE) are then applied to demonstrate error-free NRZ signaling at 25Gb/s over the rehabilitated link.
UR - https://www.scopus.com/pages/publications/84873308919
M3 - Contribución a la conferencia
AN - SCOPUS:84873308919
SN - 9781622766451
T3 - DesignCon 2012: Where Chipheads Connect
SP - 1166
EP - 1186
BT - DesignCon 2012
Y2 - 30 January 2012 through 2 February 2012
ER -