TY - GEN
T1 - An IC Mixed-Signal Framework for Design, Optimization, and Verification of High-Speed Links
AU - Madrigal-Boza, Gabriel
AU - Oviedo-Hernandez, Marco
AU - Carmona-Cruz, Allan
AU - Chavarria-Zamora, Luis A.
AU - Leon-Gamboa, Daniel
AU - Kohkemper, Daniel
AU - Garcia-Ramirez, Ronny
AU - Chacon-Rodriguez, Alfonso
AU - Rimolo-Donadio, Renato
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/2
Y1 - 2020/2
N2 - High-speed serial interfaces are ubiquitous in modern electronic systems; therefore, the design of application specific integrated circuits must often consider their incorporation. This is not a straightforward task since electromagnetic interactions among complex circuits and the influence of off-chip interconnects must be considered. This work presents an automated design, optimization, and pre-silicon verification framework for this type of interfaces, considering a mixed-signal IC environment coupled to a channel simulator through S-parameter models. An application scenario for the optimization of a CTLE stage for USB 3.0 channels is discussed to exemplify the viability of the presented approach.
AB - High-speed serial interfaces are ubiquitous in modern electronic systems; therefore, the design of application specific integrated circuits must often consider their incorporation. This is not a straightforward task since electromagnetic interactions among complex circuits and the influence of off-chip interconnects must be considered. This work presents an automated design, optimization, and pre-silicon verification framework for this type of interfaces, considering a mixed-signal IC environment coupled to a channel simulator through S-parameter models. An application scenario for the optimization of a CTLE stage for USB 3.0 channels is discussed to exemplify the viability of the presented approach.
KW - Differential Signaling
KW - Equalization
KW - High-Speed Serial Link
KW - Interconnect
KW - Mixed-Signal Design
KW - S-Parameters
UR - https://www.scopus.com/pages/publications/85084315809
U2 - 10.1109/LASCAS45839.2020.9068985
DO - 10.1109/LASCAS45839.2020.9068985
M3 - Contribución a la conferencia
AN - SCOPUS:85084315809
T3 - 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
BT - 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020
Y2 - 25 February 2020 through 28 February 2020
ER -