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A 16-bit Pressure Sensing Interface Integrating a 460 fJ/conv Incremental Sigma Delta ADC for Medical Devices

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This work presents an incremental 2nd-order sigma delta using a single operational transconductance amplifier. This design provides a good trade-off between time conversion, high bit resolution, power consumption and area utilization for a pressure sensing reading interface. The modulator, designed in 180 nm CMOS technology, has been optimized for low area utilization, occupying only 0.058 mm2. Post-layout simulations were performed showing a resolution of 150 μV while consuming 120 μW and 460 fJ/conv. The system has a resolution of 16 bits, a bandwidth of 2 kHz, an oversampling ratio of 512 and a sampling frequency of 2 MHz.

Original languageEnglish
Title of host publication2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728134277
DOIs
StatePublished - Feb 2020
Event11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020 - San Jose, Costa Rica
Duration: 25 Feb 202028 Feb 2020

Publication series

Name2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020

Conference

Conference11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020
Country/TerritoryCosta Rica
CitySan Jose
Period25/02/2028/02/20

Keywords

  • CMOS
  • Incremental analog-to-digital converter (IADC)
  • low-area
  • low-power
  • sigma delta modulation

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