Generación Automática de Hardware para Aplicaciones de Aprendizaje Automático basadas en FPGA

The current research project proposal focuses on the automatic development of hardware that enables the execution of machine learning applications, specifically deep neural networks (DNNs), for deployment on resource-constrained FPGAs. FPGAs, being configurable circuits, are crucial for enabling real-time data processing in applications like IoT and autonomous edge systems.
Within the context of constrained FPGAs, where resources such as available energy and memory are limited, the proposal of this project leverages the concept of approximate computing. This involves sacrificing a small degree of precision in calculations to achieve enhanced performance and efficiency, which aligns perfectly with the limitations of edge devices. The proposed approach involves designing automated tools that create optimized approximate hardware circuits for specific tasks at the edge, including the execution of DNNs. By assessing application requirements and sensitivity to errors, these tools will intelligently configure FPGA architectures, striking an optimal balance between precision and performance.
By harnessing the use of High-Level Synthesis (HLS), hardware blocks for different trade-offs will be generated from C++ models of individual components required by DNNs. These trade-offs encompass FPGA resources, result precision, and execution cycles, which will be used to build accelerators for these applications. Based on these blocks and their descriptions, models for quick estimation of precision and resources will be developed, and real-time precision configuration will be explored. Additionally, the DNN accelerators developed through this project will be integrated with general-purpose processors for execution on commercial platforms that offer the CPU+FPGA combination.

Diseñar bloques de hardware parametrizables para arquitecturas de DNNs en FPGAs.

Sistemas empotrados